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| CS4390 24-Bit, Stereo D/A Converter for Digital Audio Features Description The CS4390 is a complete stereo digital-to-analog output system. In addition to the traditional D/A function, the CS4390 includes a digital interpolation filter followed by an 128X oversampled delta-sigma modulator. The modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 1 and 50 kHz while maintaining linear phase response simply by changing the master clock frequency. The CS4390 also includes an extremely flexible serial port utilizing mode select pins to support multiple interface formats. The master clock can be either 256, 384, or 512 times the input sample rate, supporting various audio environments. ORDERING INFORMATION CS4390-KP -10 to 70 C CS4390-KS -10 to 70 C CDB4390 VA 3 VD 6 l 24-Bit Conversion l 115 dB Signal-to-Noise-Ratio (EIAJ) l Complete Stereo DAC System -- 128X Interpolation Filter -- Delta-Sigma DAC -- Analog Post Filter l 106 dB Dynamic Range l Low Clock Jitter Sensitivity l Filtered Line-Level Outputs l Adjustable System Sampling Rates 48 kHz l Pin-compatible with the CS4329 I -- Linear Phase Filtering -- Zero Phase Error Between Channels -- including 32 kHz, 44.1 kHz & 48 kHz l Digital De-emphasis for 32 kHz, 44.1 kHz, & 20-pin Plastic DIP 20-pin Plastic SSOP Evaluation Board DIF0 DIF1 DIF2 20 LRCK SCLK SDATA 7 9 10 Serial Input Interface 19 12 DEM0 1 DEM1 2 De-emphasis Voltage Reference 16 MUTE_L Interpolator Delta-Sigma Modulator DAC Analog Low-Pass Filter AOUTL+ 18 AOUTL17 AUTO_MUTE 11 Interpolator Delta-Sigma Modulator 8 MCLK DAC Analog Low-Pass Filter 15 MUTE_R AOUTR+ 14 AOUTR13 5 DGND 4 AGND Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved) JUN `98 DS264F1 1 CS4390 ANALOG CHARACTERISTICS (TA = 25C; Full-Scale Differential Output Sine wave, 997 Hz; Fs = 48 kHz; Input Data = 24 Bits; SCLK = 3.072 MHz; MCLK = 12.288 MHz; RL = 20 k differential; VD = VA = 5 V; Logic "1" = VD; Logic "0" = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted unless otherwise specified.) Parameter Specified Temperature Operating Range Dynamic Performance Dynamic Range 24-Bit 20-Bit (A-Weighted) 16-Bit Total Harmonic Distortion + Noise 24-Bit (A-Weighted) (Note 1) 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (Note 2) THD+N -90 -78 -38 0 26.23 75 IA ID IA+ID -98 -83 -43 -98 -83 -43 -93 -74 -34 115 -110 0.1 0.5 25/Fs 0.1 2 200 30 12 42 500 210 2.5 60 21.77 0.001 +0.3/-0.3 +0.2/-0.4 +0.1/-0.45 5 45 225 dB dB dB dB dB dB dB dB dB dBFS dB dB deg kHz dB kHz dB s dB dB dB dB % ppm/C mA mA mA A mW mW dB Symbol TA (Note 1) (A-Weighted) Min -10 98 101 Typ 103 106 103 106 94 96 Max 70 Unit C dB dB dB dB dB dB 20-Bit 16-Bit Idle Channel Noise / Signal-to-Noise-Ratio Interchannel Isolation (1 kHz) Combined Digital and Analog Filter Characteristics Frequency Response 10 Hz to 20 kHz (Note 3) Deviation from linear phase Passband: to -0.1 dB corner (Note 3) Passband Ripple StopBand (Note 3) StopBand Attenuation (Note 3) Group Delay (Note 4) De-emphasis Error (referenced to 1 kHz) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Power Supplies Power Supply Current: Normal Operation Power Dissipation Power Supply Rejection Ratio (1 kHz) Power-down Normal Operation Power-down PSRR 2 DS264F1 CS4390 ANALOG CHARACTERISTICS (CONTINUED) Parameter Analog Output Differential Full Scale Output Voltage Output Common Mode Voltage Differential Offset AC Load Resistance Load Capacitance Notes: 1. Triangular PDF Dithered Data 2. AUTO-MUTE active. See parameter definitions 3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz, the passband edge is 0.4535xFs and the stopband edge is 0.5465xFs. 4. Group Delay for Fs=48 kHz 25/48 kHz=520 s 5. Specified for a fully differential output ((AOUT+)-(AOUT-)). See Figure 12. Symbol (Note 5) Min 1.90 4 Typ 2.0 2.2 3 Max 2.10 15 100 Unit Vrms V mV k pf RL CL SWITCHING CHARACTERISTICS 1 = VD = VA = 5.25 to 4.75 Volts; CL = 20 pF) Parameter Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low External SCLK Mode SCLK Pulse Width Low SCLK Pulse Width High SCLK Period (TA= -10 to 70C; Logic 0 = AGND = DGND; Logic Symbol Fs Min 1 10 10 21 21 31 32 20 20 1------------------128 ( Fs ) MCLK / LRCK = 512 MCLK / LRCK = 512 MCLK / LRCK = 384 MCLK / LRCK = 384 MCLK / LRCK = 256 MCLK / LRCK = 256 tsclkl tsclkh tsclkw tslrd tslrs tsdlrs tsdh tsclkw tsdlrs tsdh tsdh Typ - Max 50 - Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time Internal SCLK Mode SCLK Period SCLK / LRCK = 64 SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time 512 SCLK rising to SDATA hold time MCLK / LRCK = 256 or MCLK / LRCK = 384 20 20 20 20 1---------------64 ( Fs ) 1------------------- + 10 512 ( Fs ) 1------------------- + 15 512 ( Fs ) 1------------------- + 15 384 ( Fs ) DS264F1 3 CS4390 LRCK t slrs t slrd t sclkl t sclkh SCLK t sdh t sdlrs SDATA External Serial Mode Input Timing LRCK SDATA t sclkw t sdlrs t sdh *INTERNAL SCLK Internal Serial Mode Input Timing * The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4390. 4 DS264F1 CS4390 DIGITAL CHARACTERISTICS (TA = 25C; VD = 5 V 5%) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Digital Input Capacitance Symbol VIH VIL Vin Min 2.0 Typ 10 Max 0.8 10.0 Unit V V A pF ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.) Parameter DC Power Supply: Positive Analog Positive Digital |VA - VD| Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VD Iin VIND TA Tstg Min -0.3 -0.3 0.0 -0.3 -55 -65 Max 6.0 6.0 0.4 10 (VD)+0.4 125 150 Unit V V V mA V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground) Parameter DC Power Supply: Positive Digital Positive Analog |VA - VD| Symbol VD VA Min 4.75 4.75 Typ 5.0 5.0 Max 5.25 5.25 0.4 Unit V V V DS264F1 5 CS4390 10 + 1 F 0.1 F 6 VD DIF0 DIF1 DIF2 LRCK SCLK* SDATA + 1 F 3 VA AOUTL17 0.1 F +5V Analog 20 Mode Select 19 12 7 9 10 CS4390 AOUTL+ 18 Analog Conditioning Audio Data Processor 1 2 15 16 11 8 DEM0 DEM1 MUTE_R AOUTR- 13 Analog Conditioning MUTE_L AUTO_MUTE MCLK DGND AGND 4 5 AOUTR+ 14 External Clock * SCLK must be connected to DGND for operation in Internal SCLK Mode Figure 1. Typical Connection Diagram 6 DS264F1 CS4390 GENERAL DESCRIPTION The CS4390 is a complete stereo digital-to-analog system including 128x digital interpolation, fourthorder delta-sigma digital-to-analog conversion, 128x oversampled one-bit delta-sigma modulator and analog filtering. This architecture provides a high insensitivity to clock jitter. The DAC converts digital data at any input sample rate between 1 and 50 kHz, including the standard audio rates of 48, 44.1 and 32 kHz. The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of laser trimmed resistive DAC architectures by using an inherently linear 1-bit DAC. The advantages of a 1bit DAC include: ideal differential linearity, no distortion mechanisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values. of the input signal at multiples of 128x the input sample rate. These images are removed by the external analog filter. Delta-Sigma Modulator The interpolation filter is followed by a fourth-order delta-sigma modulator which converts the 24bit interpolation filter output into 1-bit data at 128x Fs. Switched-Capacitor Filter The delta-sigma modulator is followed by a digitalto-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is determined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit signal. This technique greatly reduces the sensitivity to clock jitter and is a major improvement over earlier generations of 1-bit digitalto-analog converters where the magnitude of charge in the D-to-A process is determined by switching a current reference for a period of time defined by the master clock. The CS4390 incorporates a differential output to maximize the output level to minimize the amount of gain required in the output analog stage. The differential output also allows for the cancellation of common mode errors in the differential to singledended converter. Digital Interpolation Filter The digital interpolation filter increases the sample rate by a factor of 4 and is followed by a 32x digital sample-and hold to effectively achieve a 128x interpolation filter. This filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate, Fs. This allows for the selection of a less complex analog filter based on outof-band noise attenuation requirements rather than anti-image filtering. Following the interpolation filter, the resulting frequency spectrum has images Interpolator Delta-Sigma Modulator DAC Analog Low-Pass Filter AOUTL+ AOUTL- Figure 2. Block Diagram DS264F1 7 CS4390 SYSTEM DESIGN Master Clock The Master Clock, MCLK, is used to operate the digital interpolation filter and the delta-sigma modulator. MCLK must be either 256x, 384x or 512x the desired Input Sample Rate, Fs. Fs is the frequency at which digital audio samples for each channel are input to the DAC and is equal to the LRCK frequency. The MCLK to LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are then set to generate the proper clocks for the digital filter, delta-sigma modulator and switched-capacitor filter. LRCK must be synchronous with MCLK. Once the MCLK to LRCK frequency ratio has been detected, the phase and frequency relationship between the two clocks must remain fixed. If during any LRCK this relationship is changed, the CS4390 will reset. Table 1 illustrates the standard audio sample rates and the required MCLK frequencies. Fs (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 MCLK (MHz) 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 Format 0 1 2 3 4 5 6 Calibrate Figure 3 3 3 4 5 6 7 - Table 2. Digital Input Formats Formats 0, 1, and 2 are shown in Figure 3. The audio data is right-justified, LSB aligned with the trailing edge of LRCK, and latched into the serial input data buffer on the rising edge of SCLK. Formats 0, 1, and 2 are 16, 24, and 20-bit versions, respectively, and differ only in the number of data bits required. Format 1 in the CS4390 is not compatible with Format 1 in the CS4329. Formats 3 and 4 are 24-bit left justified, MSB aligned with the leading edge of LRCK, and are identical with the exception of the SCLK edge used to latch data. Data is latched on the falling edge of SCLK in Format 3 and the rising edge of SCLK in Format 4. Both formats will support 16, 18, and 20bit inputs if the data is followed by 8, 6, or 4 zeros to simulate a 24-bit input as shown in Figures 4 and 5. A very small offset will result if the 20, 18, or 16bit data is followed by static non-zero data. Formats 5 and 6 are compatible with the I2S serial data protocol and are shown in Figures 6 and 7. Notice that the MSB is delayed 1 period of SCLK following the leading edge of LRCK and LRCK is inverted compared to the previous formats. Data is latched on the rising edge of SCLK. Format 5 is 16bit I2S while Format 6 is 24-bit I2S. 20, 18, or 16bit I2S can be implemented in Format 6 if the data is followed by 4, 6, or 8 zeros respectively to simulate a 24-bit input as shown in Figure 7. A very small offset will result if the 20, 18, or 16-bit data is followed by static non-zero data. Table 1. Common Clock Frequencies Serial Data Interface The Serial Data interface is accomplished via the serial data input, SDATA, serial data clock, SCLK, and the left/right clock, LRCK. The CS4390 supports seven serial data formats which are selected via the digital input format pins DIF0, DIF1 and DIF2. The different formats control the relationship of LRCK to the serial data and the edge of SCLK used to latch the data into the input buffer. Table 2 lists the seven formats, along with the associated figure number. The serial data is represented in 2's-complement format with the MSB-first in all seven formats. 8 DS264F1 DS264F1 NOTE: Format 1 is not compatible with CS4329 Figure 3. Digital Input Format 0, 1 and 2. Figure 4. Digital Input Format 3. CS4390 9 10 Figure 5. Digital Input Format 4. Figure 6. Digital Input Format 5. CS4390 DS264F1 Figure 7. Digital Input Format 6. CS4390 Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4390 supports both external and internal serial clock generation modes. De-Emphasis Implementation of digital de-emphasis requires reconfiguration of the digital filter to maintain the filter response shown in Figure 8 at multiple sample rates. The CS4390 is capable of digital de-emphasis for 32, 44.1 or 48kHz sample rates. Table 3 shows the de-emphasis control inputs for DEM 0 and DEM 1. DEM 1 0 0 1 1 DEM 0 0 1 0 1 De-emphasis 32 kHz 44.1 kHz 48 kHz OFF External Serial Clock The CS4390 will enter the external serial clock mode if 15 or more high\low transitions are detected on the SCLK pin during any phase of the LRCK period. When this mode is enabled, internal serial clock mode cannot be accessed without returning to the power down mode. Internal Serial Clock In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK. The internal SCLK / LRCK ratio is always 64 and operation in this mode is identical to operation with an external serial clock synchronized with LRCK. The SCLK pin must be connected to DGND for proper operation. The internal serial clock mode is advantageous in that there are situations where improper serial clock routing on the printed circuit board can degrade system performance. The use of the internal serial clock mode simplifies the routing of the printed circuit board by allowing the serial clock trace to be deleted and avoids possible interference effects. Table 3. De-Emphasis Filter Selection Gain dB T1 = 50 s 0dB -10dB T2 = 15 s F1 3.183 kHz F2 Frequency 10.61 kHz Figure 8. De-emphasis Filter Response Mute Functions The CS4390 includes an auto-mute function which will initiate a mute if 8192 consecutive 0's or 1's are input on both the Left and Right channels. The mute will be released when non-static input data is applied to the DAC. The auto-mute function is useful for applications, such as compact disk players, where the idle channel noise must be minimized. This feature is active only if the AUTO_MUTE pin is low and is independent of the status of MUTE_L and MUTE_R. Either channel can also be muted instantaneously with the MUTE_L or MUTE_R. DS264F1 Initialization, Calibration and Power-Down Upon initial power-up, the DAC enters the powerdown mode. The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, one-bit D/A converters and switched-capacitor low-pass filters are powered down. The device will remain in the power-down mode until MCLK and LRCK are presented. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. The phase and frequency relationship between the two clocks must remain fixed. If during any LRCK this relationship 11 CS4390 is changed, the CS4390 will reset. Power is applied to the internal voltage reference, the D/A converters, switched-capacitor filters and the DAC will then enter a calibration mode to properly set the common mode bias voltage and minimize the differential offset. This initialization and calibration sequence requires approximately 2700 cycles of LRCK. A offset calibration can also be invoked by taking the Format select pins, DIF0, DIF1 and DIF2, to a logic 1 as shown in Table 2. During calibration, the differential outputs are shorted together and the common-mode voltage appears at the output with approximately an 8 kohm output impedance. Following calibration, the analog output impedance becomes less than 10 ohms and the common mode voltage will move to approximately 2.2 V . The CS4390 will enter the power-down mode, within 1 period of LRCK, if either MCLK or LRCK is removed. The initialization sequence, as described above, occurs when MCLK and LRCK are restored. 0 -10 -20 -30 -40 -50 -60 Magnitude (dB) -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Frequency (x Fs) 0.9 1.0 Figure 9. CS4390 Combined Digital and Analog Filter Stopband Rejection 0 -10 -20 -30 Magnitude (dB) -40 -50 -60 -70 -80 -90 Combined Digital and Analog Filter Response The frequency response of the combined analog switched-capacitor and digital filters is shown in Figures 9, 10 and 11. The overall response is clock dependent and will scale with Fs. Note that the response plots have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs, such as 48 kHz. -100 0.45 0.48 0.51 0.54 Frequency (x Fs) 0.57 0.60 Figure 10. CS4390 Combined Digital and Analog Filter 0 -1 -2 Magnitude (dB) -3 -4 -5 -6 -7 -8 -9 Analog Output and Filtering The analog output should be operated in a differential mode which allows for the cancellation of common mode errors including noise, distortion and offset voltage. Each output will produce a nominal 2.83 Vpp (1 Vrms) output for a full scale digital input which equates to a 5.66 Vpp (2Vrms) differential signal as shown in Figure 12. -10 0.46 0.47 0.48 0.49 0.50 Frequency (x Fs) 0.51 0.52 Figure 11. Combined Digital and Analog Filter 12 DS264F1 CS4390 Figure 13 displays the CS4390 output noise spectrum. The noise beyond the audio band can be further reduced with additional analog filtering. The applications note "Design Notes for a 2-Pole Filter with Differential Input " discusses the second-order Butterworth filter and differential to signal-ended converter which was implemented on the CS4390 evaluation board, CDB4390. The CS4390 filter is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. CS4390 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4390 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangements with VA connected to a clean +5volt supply. VD should be derived from VA through a 10 resistor. VD should not be used to power additional digital circuitry. All mode pins which require VD should be connected to pin 6 of the CS4390. All mode pins which require DGND should be connected to pin 5 of the CS4390. Pins 4 and 5, AGND and DGND, should be connected together at the CS4390. DGND for the CS4390 should not be confused with the ground for the digital section of the system. The CS4390 should be positioned over the analog ground plane near the digital/analog ground plane split. The analog and digital ground planes must be connected elsewhere in the system. The CS4390 evaluation board, CDB4390, demonstrates this layout technique. This technique minimizes digital noise and insures proper power supply matching and sequencing. Decoupling capacitors should be located as near to the CS4390 as possible. (2.2 + 1.4)V AOUT+ 2.2V (2.2 - 1.4)V (2.2 + 1.4)V AOUT2.2V (2.2 - 1.4)V Full Scale Input level= (AIN+) - (AIN-)= 5.66 Vpp Figure 12. Full Scale Input Voltage 0 -20 -40 Performance Plots The following collection of CS4390 measurement plots were taken from the CDB4390 evaluation board using the Audio Precision Dual Domain System Two. Figure 14 shows the frequency response at a 48 kHz sample rate. The response is flat to 20 kHz +/-0.1 dB as specified. 0 .25 .50 .75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 Frequency (x Fs) Magnitude (dB) -60 -80 -100 -120 -140 -160 Figure 13. CS4390 Output Noise Spectrum Figure 15 shows THD+N versus signal amplitude for a 1 kHz 24-bit dithered input signal. Notice that the there is no increase in distortion as the signal level decreases. This indicates very good low-level linearity, one of the key benefits of delta-sigma digital to analog conversion. DS264F1 13 CS4390 Figure 16 shows a 16 k FFT of a 1 kHz full-scale input signal. The signal has been filtered by a notch filter within the System Two to remove the fundamental component of the signal. This minimizes the distortion created in the analyzer analog-to-digital converter. This technique is discussed by Audio Precision in the 10th anniversary addition of AUDIO.TST. Figure 17 shows a 16 k FFT of a 1 kHz -20 dBFS input signal. The signal has been filtered by a notch filter within the System Two to remove the fundamental component of the signal. Figure 18 shows a 16 k FFT of a 1 kHz -60 dBFS input signal. Figure 19 shows the fade-to-noise linearity. The input signal is a dithered 24-bit 500 Hz sine wave which fades from -60 to -120 dBFS. During the fade, the output from the CS4390 is measured and compared to the ideal level. Notice the very close tracking of the output level to the ideal, even at low level inputs. The gradual shift of the plot away from zero at signals levels < -110 dB is caused by the background noise starting to dominate the measurement. 14 DS264F1 CS4390 +1 +0.8 +0.6 +0.4 d B r +0 A +0.2 -60 -65 -70 -75 -80 d -85 B r -90 A -95 -100 -105 -0.2 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k Hz 2k 5k 10k 20k -110 -115 -120 -60 -50 -40 -30 dBFS -20 -10 +0 Figure 14. Frequency Response +0 -10 -20 -30 -40 -50 -60 d -70 B r -80 A -90 -100 -110 -120 -130 -140 -150 -160 2.5k 5k 7.5k 10k Hz 12.5k 15k 17.5k 20k +0 -10 -20 -30 -40 -50 -60 d -70 B r -80 A -90 -100 -110 -120 -130 -140 -150 -160 Figure 15. THD+N vs. Amplitude 2.5k 5k 7.5k 10k Hz 12.5k 15k 17.5k 20k Figure 16. 0 dBFS FFT +0 -10 -20 -30 -40 -50 -60 d B -70 r -80 A -90 -100 -110 -120 -130 -140 -150 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k Figure 17. -20 dBFS FFT +5 +4 +3 +2 d +1 B r -0 A -1 -2 -3 -4 -5 -120 -100 -80 -60 dBFS -40 -20 +0 Figure 18. -60 dBFS FFT Figure 19. Fade-to-Noise Linearity DS264F1 15 CS4390 PIN DESCRIPTIONS PDIP and SSOP DEM0 DEM1 VA AGND DGND VD LRCK MCLK SCLK SDATA 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DIF0 DIF1 AOUTL+ AOUTLMUTE_L MUTE_R AOUTR+ AOUTRDIF2 AUTO-MUTE Power Supply Connections VA - Positive Analog Power, PIN 3. Positive analog supply. Nominally +5 volts. VD - Positive Digital Power, PIN 6. Positive supply for the digital section. Nominally +5 volts. AGND - Analog Ground, PIN 4. Analog ground reference. DGND - Digital Ground, PIN 5. Digital ground for the digital section. Analog Outputs AOUTR+,AOUTR- - Differential Right Channel Analog Outputs, PIN 14, PIN 13. Analog output connections for the Right channel differential outputs. Nominally 2 Vrms (differential) for full-scale digital input signal. AOUTL+,AOUTL- - Differential Left Channel Analog Outputs, PIN 18, PIN 17. Analog output connections for the Left channel differential outputs. Nominally 2 Vrms (differential) for full-scale digital input signal. 16 DS264F1 CS4390 Digital Inputs MCLK - Clock Input, PIN 8. The frequency must be either 256x, 384x or 512x the input sample rate (Fs). LRCK - Left/Right Clock, PIN 7. This input determines which channel is currently being input on the Serial Data Input pin, SDATA. The format of LRCK is controlled by DIF0, DIF1 and DIF2. SCLK - Serial Bit Input Clock, PIN 9. Clocks the individual bits of the serial data in from the SDATA pin. The edge used to latch SDATA is controlled by DIF0, DIF1 and DIF2. SDATA - Serial Data Input, PIN 10. Two's complement MSB-first serial data of either 16, 18, 20 or 24 bits is input on this pin. The data is clocked into the CS4390 via the SCLK clock and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0, DIF1 and DIF2. DIF0, DIF1, DIF2 - Digital Input Format, PINS 20, 19, 12 These three pins select one of seven formats for the incoming serial data stream. These pins set the format of the SCLK and LRCK clocks with respect to SDATA. The formats are listed in Table 2. DEM0, DEM1 - De-Emphasis Select, PINS 1, 2. Controls the activation of the standard 50/15us de-emphasis filter for either 32, 44.1 or 48 kHz sample rates. AUTO-MUTE - Automatic Mute on Zero-Data, PIN 11. When Auto-Mute is low the analog outputs are muted following 8192 consecutive LRCK cycles of static 0 or 1 data. Mute is canceled with the return of non-static input data. MUTE_R , MUTE_L Mute, PINS 15, 16. MUTE_L low activates a muting function for the Left channel. MUTE_R low activates a muting function for the Right channel. DS264F1 17 CS4390 PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. De-Emphasis Error A measure of the difference between the ideal de-emphasis filter and the actual de-emphasis filter response. Measured from 10 Hz to 20 kHz relative to 1 kHz. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. 18 DS264F1 CS4390 PACKAGE DIMENSIONS 20L SSOP PACKAGE DRAWING N D E11 A2 A1 L E A e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.272 0.291 0.197 0.022 0.025 0 MAX 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.030 0.041 8 MILLIMETERS MIN -0.05 1.62 0.22 6.90 7.40 5.00 0.55 0.63 0 MAX 2.13 0.25 1.88 0.38 7.50 8.20 5.60 0.75 1.03 8 NOTE 2,3 1 1 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. DS264F1 19 CS4390 20 PIN PLASTIC (PDIP) PACKAGE DRAWING eB D E1 1 SEATING PLANE e b A2 A A1 b1 L E eC TOP VIEW eA c BOTTOM VIEW SIDE VIEW INCHES DIM A A1 A2 b b1 c D E E1 e eA eB eC L MIN 0.000 0.015 0.115 0.014 0.045 0.008 0.980 0.300 0.240 0.090 0.280 0.300 0.000 0.115 0 MAX 0.210 0.025 0.195 0.022 0.070 0.014 1.060 0.325 0.280 0.110 0.320 0.430 0.060 0.150 15 MILLIMETERS MIN MAX 0.00 5.33 0.38 0.64 2.92 4.95 0.36 0.56 1.14 1.78 0.20 0.36 24.89 26.92 7.62 8.26 6.10 7.11 2.29 2.79 7.11 8.13 7.62 10.92 0.00 1.52 2.92 3.81 0 15 20 DS264F1 * Notes * |
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